In a design of a semiconductor integrated circuit, timing verification for determining whether or not data transfer is normally performed is performed. In the timing verification, between two sequential circuits, for example, Flip Flops (hereinafter, described as FF), where data transfer is performed, a data path delay and a clock path delay are calculated in consideration of the electric characteristic of the semiconductor integrated circuit at an operation time. For example, it is checked whether or not data is transferred within a certain clock cycle (setup timing check), or it is checked whether or not data transfer is too early (hold timing check).
Related art is disclosed in Japanese Laid-open Patent Publication No. 2001-273338, Japanese Laid-open Patent Publication No. 6-174781, or the like.